The present invention relates to a method of manufacturing an insulated-gate field-effect transistor device which is suitable for large scale integrated circuits.
In large scale integration, it is necessary to minimize the size of insulated-gate field-effect transistors (hereinafter referred to as "MOS transistors") in order to fabricate an integrated circuit of high density. However, as an MOS transistor is decreased in size, the channel between its source and drain is shortened and the threshold voltage for inverting the channel region decreases, which results in poorer switching characteristics. This phenomenon is called "short channel effect." For example, in the manufacture of MOS transistors, the source and drain regions are generally formed by diffusing impurities. If the source and drain regions are formed deeply, then impurities may be diffused into the channel regions to reduce the effective channel length resulting in the so-called short channel effect.
To prevent the short channel effect, it is necessary to make the source and drain regions shallow. On the other hand, the source and drain regions normally must have a small resistance for high speed operation of the MOS transistor and a high impurity concentration for good ohmic contact with the electrodes mounted on these regions.
It is difficult to form source and drain regions of high impurity density and a small depth by using known diffusion and ion implantation techniques. The reason for this is that the introduction of impurities into the silicon substrate is followed by heating the silicon substrate at 900.degree. C. or higher in order to activate the impurities, which further diffuses the impurities. Also, if the impurity density is high in the drain region, then hot electrons may be produced due to the concentration of an electric field in the vicinity of the PN junction formed between the drain region and the silicon substrate. These hot electrons may be trapped in the gate insulating film of the MOS transistor and thereby change the threshold voltage of the MOS transistor.
A known technique to prevent injection of such hot electrons is to form each of the source and drain regions in two layers of different impurity concentrations. More specifically, each of the source and drain regions includes a first layer of low impurity concentration and small depth and a second layer formed in the first layer. The second layer has a high impurity concentration and a depth smaller than that of the first layer. The first and second layers are normally formed by ion implantation so that the dose and depth of impurities introduced into the silicon substrate can be easily controlled. In such an MOS transistor, the first layer of low impurity concentration decreases the electric field in the vicinity of the PN junction between the drain region and the silicon substrate to suppress injection of hot electrons.
In the manufacture of the above MOS transistor, after formation of each of the first and second layers, the substrate is heated at a high temperature of 900.degree. C. or higher to lower the resistance of the source and drain regions and to provide good ohmic contact with the electrodes. However, the repetitive heating of the substrate at such a high temperature causes the first layer to diffuse deeper into the substrate and makes it difficult to form a second layer of high impurity concentration and small depth. As a result, it is difficult to minimize the size of the MOS transistor and prevent the occurrence of the short channel effect.